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MAX1497/MAX1499
3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and C Interface
12
______________________________________________________________________________________
Digital Filtering
The MAX1497/MAX1499 contain an on-chip digital low-
pass filter that processes the data stream from the
modulator using a SINC4 response:
The SINC4 filter has a settling time of four output data
periods (4 x 200ms).
The MAX1497/MAX1499 have 25% overrange capabili-
ty built into the modulator and digital filter. The digital fil-
ter is optimized for the fCLK equal to 4.9152MHz. Other
clock frequencies can be used; however, 50Hz/60Hz
noise rejection decreases. The frequency response of the
SINC4 filter is calculated as follows:
where N is the oversampling ratio, and fm = N x output
data rate = 5Hz.
Filter Characteristics
Figure 2 shows the filter frequency response. The
SINC4 characteristic -3dB cutoff frequency is 0.228
times the first notch frequency (5Hz). The oversampling
ratio (OSR) for the MAX1497 is 128 and the OSR for the
MAX1499 is 1024.
The output data rate for the digital filter corresponds to
the positioning of the first notch of the filter’s frequency
response. The notches of the SINC4 filter are repeated
at multiples of the first notch frequency. The SINC4 filter
provides an attenuation of better than 100dB at these
notches. For example, 50Hz is equal to 10 times the
first notch frequency and 60Hz is equal to 12 times the
first notch frequency.
For large step changes at the input, allow a settling
time of 800ms before valid data is read.
Clock Modes
Configure the MAX1497/MAX1499 to use either the
internal oscillator or an externally applied clock to drive
the modulator and filter. Set the EXTCLK bit in the con-
trol register to zero to put the device in internal-clock
mode. Set the EXTCLK bit to one to put the device in
Hz
N
Z
Hf
N
f
N
m
()
sin
=
=
1 1
1
4
-
π
sin( )
x
4
MAX1499
BINARY-TO-
BCD
CONVERTERS
ADC
LED
DRIVER
INPUT
BUFFERS
-2.5V
AIN+
AIN-
REF+
REF-
+2.5V
AVDD
DVDD
GLED
2.048V
BANDGAP
REFERENCE
OSCILLATOR
CLOCK
SCLK
DIN
DOUT
EOC
SEG1
SEGF
SEGDP
DIG0
DIG4
CLK
CS
SERIAL I/O AND CONTROL
+2.5V
2.048V
GND
A = 1.22
TO
CONTROL
CHARGE
PUMP
-2.5V
LOWBATT
VNEG
LED_EN
VLED
ISET
Figure 1. MAX1499 Functional Diagram
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